1. Field of the Invention
This invention relates to the fabrication of bipolar and MOS devices on an integrated circuit substrate. More particularly, this invention relates to the production of a fast bipolar transistor and an at least one MOS transistor on the same substrate using raised polysilicon contacts for at least some of the electrodes.
2. Description of the Prior Art
In the construction of integrated circuits, the active devices usually comprises either bipolar or MOS type devices. Bipolar devices may be chosen instead of MOS due to their high current carrying characteristics and superior transconductance of the devices. On the other hand, the use of MOS devices, in preference to bipolar devices, usually occurs when either the low power consumption or high density characteristics of MOS devices are needed or desired.
In many instances, it would be most desirable to use both types of devices in an integrated circuit structure to achieve certain desired effects, e.g., fast logic and low power storage. However, this may be difficult due to the differences in the techniques which have evolved to construct bipolar and MOS devices; particularly when such techniques may be addressed toward remedying a problem which is peculiar to one particular device.
For example, in the construction of bipolar devices, the spacing between the emitter and the base contact in prior art bipolar transistors is defined by lithography and isolated by oxide. This makes it necessary to have a high dose implanted or diffused extrinsic base region under the oxide which acts as the interconnect between the intrinsic base and the base contact. This high doping of the extrinsic base region results in unacceptable increases in capacitance between the base and the buried collector. This problem becomes particularly acute when the thickness of the epitaxial layer between the base and the buried collector is reduced for improved performance which results in the base butting against the buried collector layer to thereby raise the capacitance and slow down the speed of the device.
Furthermore, since the resistance of the doped extrinsic base region still does not approach the conductivity of polysilicon or metal, the minmum base resistance of the extrinsic base region, i.e., the resistance of the extrinsic base between the intrinsic base and the base contact, is always a factor degrading performance of such a device.
Another problem in prior art bipolar devices which adversely impacted the speed of such devices was the side diffusion of the highly doped extrinsic base into the emitter which reduced the emitter area and thereby prevented shrinking of the emitter area which would other wise be desirable to improve performance of the device by reducing the capacitance between the emitter and the intrinsic base beneath the emitter. Furthermore, in conventional emitter contruction, sidewall capacitance cannot be reduced to gain performance improvement.
Conventional construction of single crystal emitters further limits the gain of the device as well as reducing the ability to provide a shallow emitter without incurring problems of reverse injection of carriers from base to emitter.
In our prior U.S. patent application Ser. No. 747,517, filed June, 21, 1985, now U.S. Pat. No. 4,682,409, and entitled FAST BIPOLAR TRANSISTOR FOR INTEGRATED CIRCUIT STRUCTURE AND METHOD OF MAKING SAME, cross reference to which is hereby made, we described and claimed a structure having a raised polysilicon emitter contact with oxide spacers on the sidewalls and a metal silicide conductive path on the surface between the base contact and a point adjacent the oxide spacer to provide a faster device with higher gain and lower capacitance and resistance.
MOS devices are usually constructed in a non planarized fashion with steps created when making contact with the source and drain regions which are lower than the gate region. Also, despite the high density of the MOS devices, the gate contact usually occupies a large area due to the need to make the contact in a position offset to the gate region because of aligment problems.
Furthermore, in the construction of MOS devices, the source and drain junctions may be formed too deep causing the junctions to sometimes extend under the gate region causing overlap capacitance which degrades the performance of the device. The extension of the junction under the gate may be caused by forming the junction too deeply in the substrate. This can also cause the depletion region to extend sideways into the channel causing a short channel effect which further degrades the performance and functionality as well as long term reliability. If the source and drain regions can be formed as shallow junctions, which do not extend laterally, e.g., beneath the gate, the junction capacitance may also be lowered because of the reduction in the junction area.
It would, therefore, be very desirable to be able to fabricate both bipolar and MOS devices on the same substrate; preferably in a manner which would address the problems of each of the particular devices discussed above.